74F74

Features: *Guaranteed 4000V minimum ESD protectionPinoutSpecificationsStorage Temperature........................... −65°C to +150°CAmbient Temperature under Bias......... −55°C to +125°CJunction Temperature under Bias......... −55°C to +150°CVCC Pin Potential to Ground Pin ........

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74F74 Picture
SeekIC No. : 004249847 Detail

74F74: Features: *Guaranteed 4000V minimum ESD protectionPinoutSpecificationsStorage Temperature........................... −65°C to +150°CAmbient Temperature under Bias......... −55°C to +125°...

floor Price/Ceiling Price

Part Number:
74F74
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/10/30

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Product Details

Description



Features:

*Guaranteed 4000V minimum ESD protection


Pinout

  Connection Diagram


Specifications

Storage Temperature........................... −65°C to +150°C
Ambient Temperature under Bias......... −55°C to +125°C
Junction Temperature under Bias......... −55°C to +150°C
VCC Pin Potential to Ground Pin ..................−0.5V to +7.0V
Input Voltage (Note 2)................................ −0.5V to +7.0V
Input Current (Note 2).......................... −30 mA to +5.0 mA
Voltage Applied to Output
   in HIGH State (with VCC = 0V)
   Standard Output ...........................................−0.5V to VCC
   TRI-STATEÉ Output® ..................................−0.5V to +5.5V
Current Applied to Output
   in LOW State (Max)..................... twice the rated IOL (mA)
 
ESD Last Passing Voltage (Min) .................................4000V


Description

    The 74F74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering of the 74F74 occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input of the 74F74 is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input.




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