74F652

Features: *ndependent registers for A and B buses*Multiplexed real-time and stored data*Choice of non-inverting and inverting data paths-'F651 inverting-'F652 non-inverting*Guaranteed 4000V minimum ESD protectionPinoutSpecificationsStorage Temperature .........................−65°C to +150°C...

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74F652 Picture
SeekIC No. : 004249830 Detail

74F652: Features: *ndependent registers for A and B buses*Multiplexed real-time and stored data*Choice of non-inverting and inverting data paths-'F651 inverting-'F652 non-inverting*Guaranteed 4000V minimum ...

floor Price/Ceiling Price

Part Number:
74F652
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/10/30

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Product Details

Description



Features:

*ndependent registers for A and B buses
*Multiplexed real-time and stored data
*Choice of non-inverting and inverting data paths
-'F651 inverting
-'F652 non-inverting
*Guaranteed 4000V minimum ESD protection



Pinout

  Connection Diagram


Specifications

Storage Temperature .........................−65°C to +150°C
Ambient Temperature under Bias....... −55°C to +125°C
Junction Temperature under Bias .......−55°C to +175°C
                        Plastic .........................−65°C to +150°C
VCC Pin Potential to Ground Pin............... −0.5V to +7.0V
Input Voltage (Note 2)............................. −0.5V to +7.0V
Input Current (Note 2) ......................−30 mA to +5.0 mA
Voltage Applied to Output
   in HIGH State (with VCC = 0V)
   Standard Output .......................................−0.5V to VCC
   TRI-STATE Output....................................−0.5V to +5.5V
Current Applied to Output
   in LOW State (Max)..................twice the rated IOL (mA)
ESD Last Passing Voltage (Min) .............................4000V
  


Description

    The 74F652 consist of bus transceiver circuits with D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from internal registers. Data of the 74F652 on the A or B bus will be clocked into the registers as the appropriate clock pin goes to HIGH logic level. Output Enable pins (OEAB, OEBA) are provided to control the transceiver function.




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