Features: *Ideal for addressable register applications*Clock enable for address and data synchronization applications* Eight edge-triggered D flip-flops* Buffered common clock* See 'F273 for master reset version* See 'F373 for transparent latch version* See 'F374 for TRI-STATE. version* Guaranteed...
74F377: Features: *Ideal for addressable register applications*Clock enable for address and data synchronization applications* Eight edge-triggered D flip-flops* Buffered common clock* See 'F273 for master ...
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The 74F377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW.
The register of the 74F377 is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.