74F280B

Features: • High-impedance NPN base inputs for reduced loading (20A in Low and High states)• Buffered inputs - one normalized load• Word length easily expanded by cascading• Industrial temperature range available (40°C to +85°C)PinoutSpecifications SYMBOL PARAMET...

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74F280B Picture
SeekIC No. : 004249732 Detail

74F280B: Features: • High-impedance NPN base inputs for reduced loading (20A in Low and High states)• Buffered inputs - one normalized load• Word length easily expanded by cascading• ...

floor Price/Ceiling Price

Part Number:
74F280B
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/6/12

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Product Details

Description



Features:

• High-impedance NPN base inputs for reduced loading (20A in Low and High states)
• Buffered inputs - one normalized load
• Word length easily expanded by cascading
• Industrial temperature range available (40°C to +85°C)



Pinout

  Connection Diagram


Specifications

SYMBOL
PARAMETER
RATING
UNIT
VCC
Supply voltage 0.5 to +7.0 V
VIN
Input voltage 0.5 to +7.0 V
IIN
Input current 30 to +5 mA
VOUT
Voltage applied to output in High output state 0.5 toVCC V
IOUT
Current applied to output in Low output state 40 mA
Tamb
Operating free air temperature range Commercial range 0 to +70 °C
Industrial range 40 to +85 °C
Tstg
Storage temperature 65 to +150 °C



Description

The 74F280B is a 9-bit Parity Generator or Checker commonly used to detect errors in high speed data transmission or data retrieval systems. Both Even (E) and Odd (O) parity outputs are available for generating or checking even or odd parity on up to 9 bits.

The Even (E) parity output of the 74F280B is High when an even number of Data inputs (I0 - I8) are High. The Odd (O) parity output is High when an odd number of Data inputs are High.

Expansion to larger word sizes of the 74F280B is accomplished by tying the Even (E) outputs of up to nine parallel devices to the data inputs of the final stage. This expansion scheme allows an 81-bit data word to be checked in less than 20ns.




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