Features: • High impedance inputs for reduced loading (20mA in Low and High states)• Ideal buffer for MOS microprocessor or memory• Eight edgetriggered Dtype flipflops• Buffered common clock• Buffered asynchronous Master Reset• See 74F377A for clock enable versi...
74F273A: Features: • High impedance inputs for reduced loading (20mA in Low and High states)• Ideal buffer for MOS microprocessor or memory• Eight edgetriggered Dtype flipflops• Buffe...
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• High impedance inputs for reduced loading (20mA in Low and High states)
• Ideal buffer for MOS microprocessor or memory
• Eight edgetriggered Dtype flipflops
• Buffered common clock
• Buffered asynchronous Master Reset
• See 74F377A for clock enable version
• See 74F373 for transparent latch version
• See 74F374 for 3State version
SYMBOL | PARAMETER | RATING | UNIT |
VCC | Supply voltagee | 0.5 to 7.0 | V |
VIN | Input current | 0.5 to +7.0 | V |
VIN | Input current | 30 to 5 | mA |
VOUT | Voltage applied to output in High output state | 0.5 to VCC | V |
IOUT | Current applied to output in Low output state | 40 | mA |
IOUT | Operating free air temperature range | 0 to +70 | |
Tstg | Storage temperature range | 65 to 150 |
The 74F273A has eight edgetriggered Dtype flipflops with individual D inputs and Q outputs. The common uffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flipflops simultaneously.
The register of the 74F273A is fully edgetriggered. The state of each D input, one setup time before the LowtoHigh clock transition, is transferred to the corresponding flipflop's Q output.
All outputs of the 74F273A will be forced Low independently of Clock or Data inputs by a Low voltage level on the MR input. The device is useful for applications where the true output only is required and the CP and MR are common to all elements.