74F225

Features:

• Independent synchronous inputs and outputs
• Organized as 16 words of 5 bits
• DC to 25MHz data rate
• 3State outputs
• Cascadable in wordwidth and depth direction


Pinout




Description

This 80bit active element FirstInFirstOut (FIFO) of the 74F225 is a monolithic Schottkyclamped transistortransistor logic (STTL) array organized as 16words of 5bits each. A memory system using the 'F225 can be easily expanded in multiples of 16words of 5bits as shown in Figure 1. The 3State outputs controlled by a single enable input (OE) make bus connection and multiplexing simple. The 'F225 processes data in a parallel format at any desired clock rate from DC to 25MHz. Status of the 74F225 is provided by three outputs, Input Ready (IR), Unload Clock Output (UNCPOUT) and Output Ready (OR). The data outputs are noninverting with respect to the data inputs and are disabled when the OE input is High. When OE of the 74F225 is Low, the data outputs are enabled to function as totempole outputs.