74F195A

Features:

• Shift right and parallel load capability
• J K (D) inputs to first stage
• Complement output from last stage
• Asynchronous Master Reset
• Diode inputs


Pinout




Specifications

SYMBOL	PARAMETER	RATING	UNIT
VCC	Supply voltage	0.5 to +7.0	V
VIN	Input voltage	0.5 to +7.0	V
IIN	Input current	30 to +5	mA
VOUT	Voltage applied to output in high output state	0.5 to VCC	V
IOUT	Current applied to output in low output state	40	mA
Tamb	Operating free air temperature range	0 to +70	°C
Tstg	Storage temperature range	65 to +150	°C

Description

The 74F195A is a 4-Bit Parallel Access Shift Register and its functional characteristics are indicated in the Logic Diagram and Function Table. This device is useful in a variety of shifting, counting and storage applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds.

The 74F195A operates in two primary modes: shift right (Q0"Q1) and parallel load, which are controlled by the state of the Parallel Enable (PE) input. Serial data enters the first flip-flop (Q0) via the J and K inputs when the PE input is High, and is shifted one bit in the direction Q0"Q1"Q2"Q3 following each Low-to-High clock transition.

The J and K inputs of the 74F195A provide the flexibility of the J-K type input for special applications, and by tying the two together the simple D-type input is made for general applications.

The 74F195A appears as four common clocked D flip-flops when the PE input is Low. After the Low-to-High clock transition, data on the parallel inputs (D0D3) is transferred to the respective Q0Q3 outputs. Shift left operation (Q3Q2) can be achieved by tying the Qn outputs to the Dn-1 inputs and holding the PE input Low.

All parallel and serial data transfers are synchronous, occurring after each Low-to-High clock transition. The 74F195A utilizes edge-triggering, therefore there is no restriction on the activity of the J, K, Dn, and PE inputs for logic operation, other than the set-up and hold time requirements.

A Low on the asynchronous Master Reset (MR) input sets all Q outputs Low, independent of any other input condition.