74F114

Pinout




Specifications

Storage Temperature                                  -65°C to +150°C
Ambient Temperature under Bias                -55°C to +125°C
Junction Temperature under Bias                -55°C to +150°C
V_CC Pin Potential to Ground Pin                      -0.5V to +7.0V
Input Voltage (Note 2)                                    -0.5V to +7.0V
Input Current (Note 2)                              -30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V_CC = 0V)
Standard Output                                                 -0.5V to VCC
3-STATE Output                                                -0.5V to +5.5V
Current Applied to Output
in LOW State (Max)                            twice the rated I_OL (mA)
Free Air Ambient Temperature                            0°C to +70°C
Supply Voltage                                                  +4.5V to +5.5V


Description

   The 74F114 contains two high-speed JK flip-flops with common Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on S_D or C_D prevents clocking and forces Q or Q HIGH, respectively.

   Simultaneous LOW signals on S_D and C_D force both Q and Q HIGH.

   Asynchronous Inputs of the 74F114:

   LOW input to S_D sets Q to HIGH level

   LOW input to C_D sets Q to LOW level

   Clear and Set are independent of Clock

   Simultaneous LOW on C_D and S_D

   makes both Q and Q HIGH