74F113

PinoutSpecificationsAmbient Temperature under Bias -55°C to +125°CJunction Temperature under Bias -55°C to +150°CVCC Pin Potential to Ground Pin -0.5V to +7.0VInput Voltage (Note 2) -0.5V to +7.0VInput Current (Note 2) -30 mA to +5.0 mAVoltage Applied to Outputin HIGH State (with VCC = 0V)Standard...

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74F113 Picture
SeekIC No. : 004249654 Detail

74F113: PinoutSpecificationsAmbient Temperature under Bias -55°C to +125°CJunction Temperature under Bias -55°C to +150°CVCC Pin Potential to Ground Pin -0.5V to +7.0VInput Voltage (Note 2) -0.5V to +7.0VIn...

floor Price/Ceiling Price

Part Number:
74F113
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/25

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Product Details

Description



Pinout

  Connection Diagram


Specifications

Ambient Temperature under Bias                         -55°C to +125°C
Junction Temperature under Bias                         -55°C to +150°C
VCC Pin Potential to Ground Pin                               -0.5V to +7.0V
Input Voltage (Note 2)                                             -0.5V to +7.0V
Input Current (Note 2)                                      -30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output                                                        -0.5V to VCC
3-STATE Output                                                       -0.5V to +5.5V
Current Applied to Output
in LOW State (Max)                                  twice the rated IOL (mA)
Free Air Ambient Temperature                                  0°C to +70°C
Supply Voltage                                                        +4.5V to +5.5V



Description

   The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flipflop will perform according to the Truth Table as long as minimum setup and hold times are observed. Input data is transferred to the outputs on the falling edge of the clock pulse.

Asynchronous input of the 74F113:

   LOW input to SD sets Q to HIGH level

   Set is independent of clock


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