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74F109

Features: *Guaranteed 4000V minimum ESD protection.PinoutSpecificationsStorage Temperature .........................................................................................-65 to +150Ambient Temperature under Bias .......................................................................-55 t...

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SeekIC No. : 004249651 Detail

74F109: Features: *Guaranteed 4000V minimum ESD protection.PinoutSpecificationsStorage Temperature .........................................................................................-65 to +150Ambient...

74F109 Data Sheet

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Part Number:
74F109
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/23

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Product Details

Description



Features:

* Guaranteed 4000V minimum ESD protection.


Pinout

Connection Diagram


Specifications

Storage Temperature .........................................................................................-65 to +150
Ambient Temperature under Bias .......................................................................-55 to +125
Junction Temperature under Bias .......................................................................-55 to +175
   Plastic ..............................................................................................................-55 to +150
VCC Pin Potential to
   Ground Pin ........................................................................................................-0.5V to +7.0V
Input Voltage (Note 2) .........................................................................................-0.5V to +7.0V
Input Current (Note 2) ...................................................................................-30 mA to +5.0 mA
Voltage Applied to Output
   in HIGH State (with VCC = 0V)
   Standard Output ..................................................................................................-0.5V to VCC
   TRI-STATE® Output ...........................................................................................-0.5V to +5.5V
Current Applied to Output
   in LOW State (Max) ..............................................................................twice the rated IOL (mA)
ESD Last Passing Voltage (Min) ...........................................................................................4000V


Description

The 74F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design of the 74F109 allows operation as a D flip-flop (refer to 'F74 data sheet) by connecting the J and K inputs. Asynchronous Inputs:
  LOW input to SD sets Q to HIGH level
  LOW input to CD sets Q to LOW level
  Clear and Set are independent of clock
  Simultaneous LOW on CD and SD makes both Q and Q
  HIGH




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