74F1071

Features:

 18-bit array structure in 20-pin package
 FASTâ Bipolar voltage clamping action
 Dual center pin grounds for min inductance
 Robust design for ESD protection
 Low input capacitance
 Optimum voltage clamping for 5V CMOS/TTL applications


Pinout




Specifications

Storage Temperature                                            -65°C to +150°C
Ambient Temperature under Bias                          -65°C to +125°C
Junction Temperature under Bias                          -65°C to +150°C
Input Voltage (Note 2)                                                 -0.5V to +6V
Input Current (Note 2)                                       -200 mA to +50 mA
ESD (Note 3)
Human Body Model
(MIL-STD-883D method 3015.7)                                            ±10 kV
IEC 801-2                                                                                ±6 kV
Machine Model (EIAJIC-121-1981)                                           ±2 kV
DC Latchup Source Current
(JEDEC Method 17)                                                             ±500 mA
Package Power Dissipation @+70°C
SOIC Package                                                                      800 mW
Free Air Ambient Temperature                                    0°C to +70°C
Reverse Bias Voltage                                                0V to 5.25 V_DC
Thermal Resistance (q_JA in Free Air)
SOIC Package                                                                    100°C/W
SSOP Package                                                                   110°C/W


Description

   The 74F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress due to electrostatic discharge (ESD). The inputs of the device aggressively clamp voltage excursions nominally at 0.5V below and 7V above ground.