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74AUP2G80

Features: `Wide supply voltage range from 0.8 V to 3.6 V`High noise immunity`Complies with JEDEC standards:`JESD8-12 (0.8 V to 1.3 V)`JESD8-11 (0.9 V to 1.65 V)`JESD8-7 (1.2 V to 1.95 V)`JESD8-5 (1.8 V to 2.7 V)`JESD8-B (2.7 V to 3.6 V)`ESD protection:`HBM JESD22-A114-D Class 3A exceeds 5000 V`MM ...

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SeekIC No. : 004249557 Detail

74AUP2G80: Features: `Wide supply voltage range from 0.8 V to 3.6 V`High noise immunity`Complies with JEDEC standards:`JESD8-12 (0.8 V to 1.3 V)`JESD8-11 (0.9 V to 1.65 V)`JESD8-7 (1.2 V to 1.95 V)`JESD8-5 (1....

74AUP2G80 Data Sheet

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Part Number:
74AUP2G80
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

`Wide supply voltage range from 0.8 V to 3.6 V
`High noise immunity
`Complies with JEDEC standards:
`JESD8-12 (0.8 V to 1.3 V)
`JESD8-11 (0.9 V to 1.65 V)
`JESD8-7 (1.2 V to 1.95 V)
`JESD8-5 (1.8 V to 2.7 V)
`JESD8-B (2.7 V to 3.6 V)
`ESD protection:
`HBM JESD22-A114-D Class 3A exceeds 5000 V
`MM JESD22-A115-A exceeds 200 V
`CDM JESD22-C101-C exceeds 1000 V
`Low static power consumption; ICC = 0.9 mA (maximum)
`Latch-up performance exceeds 100 mA per JESD 78 Class II
`Inputs accept voltages up to 3.6 V
`Low noise overshoot and undershoot < 10 % of VCC
`IOFF circuitry provides partial Power-down mode operation
`Multiple package options
`Specified from -40 to +85 and -40 to +125


Pinout

Connection Diagram


Specifications

Symbol Parameter Conditions Min Max Unit
Vcc supply voltage   -0.5 +4.6 V
VI input voltage   - -50 V
IIk input clamping current VI < -0.5 V*1 -0.5 +4.6 V
IoK output clamping current VO < -0.5 V or VO > VCC + 0.5 V*1 - ±50 mA
VO output current VO = -0.5 V to (VCC + 0.5 V) -0.5 ±20 mA
IO supply current   - +50 mA
ICC ground current   - -50 mAc
Tstg storage temperature   -65 +150
PTOT total power dissipation Tamb = -40 to +125   250  
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For VSSOP8 packages: above 110 the value of Ptot derates linearly with 8.0 mW/K.
For XSON8 and XQFN8 packages: above 45 the value of Ptot derates linearly with 2.4 mW/K.


Description

The 74AUP2G80 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

The 74AUP2G80 ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

The 74AUP2G80 is fully specified for partial Power-down applications using IOFF.

The IOFF circuitry of the 74AUP2G80 disables the output, preventing the damaging backflow current through the device when it is powered down.

The 74AUP2G80 provides the single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock transition for predictable operation.




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