74AUP2G126

Features:

` Wide supply voltage range from 0.8 V to 3.6 V
` High noise immunity
` Complies with JEDEC standards:
   ` JESD8-12 (0.8 V to 1.3 V)
   ` JESD8-11 (0.9 V to 1.65 V)
   ` JESD8-7 (1.2 V to 1.95 V)
   ` JESD8-5 (1.8 V to 2.7 V)
   ` JESD8-B (2.7 V to 3.6 V)
` ESD protection:
   ` HBM JESD22-A114-D Class 3A exceeds 4000 V
   ` MM JESD22-A115-A exceeds 200 V
   ` CDM JESD22-C101-C exceeds 1000 V
` Low static power consumption; I<sub>CC</sub> = 0.9 mA (maximum)
` Latch-up performance exceeds 100 mA per JESD 78 Class II
` Inputs accept voltages up to 3.6 V
` Low noise overshoot and undershoot < 10 % of V_CC
` Input-disable feature allows floating input conditions
` IOFF circuitry provides partial Power-down mode operation
` Multiple package options
` Specified from -40to +85 and -40 to +125


Pinout




Specifications

Symbol	Parameter	Conditions	Min	Max	Unit
VCC	supply voltage		-0.5	+4.6	V
IIK	input clamping current	VI < 0 V	-	-50	mA
VI	input voltage	[1]	-0.5	+4.6	V
IOK	output clamping current	VO < 0 V	-	-50	mA
VO	output voltage	Active mode and Power-down mode [1]	-0.5	+4.6	V
IO	output current	VO = 0 V to VCC	-	±20	mA
ICC	supply current		-	50	mA
IGND	ground current		-	-50	mA
Tstg	storage temperature		-65	+150
Ptot	total power dissipation	Tamb = -40 to +125 [2]	-	250	mW

[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings
      are observed.
[2] For VSSOP8 packages: above 110 the value of Ptot derates linearly with 8.0 mW/K.
     For XSON8 and XQFN8 packages: above 45 the value of Ptot derates linearly with 2.4 mW/K.


Description

The 74AUP2G126 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V_CC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire V_CC range from 0.8 V to 3.6 V.

The 74AUP2G126 is fully specified for partial Power-down applications using I_OFF.

The I_OFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

The 74AUP2G126 provides the dual non-inverting buffer/line driver with 3-state output.

The 3-state output of the 74AUP2G126 is controlled by the output enable input (nOE). A LOW level at pin nOE causes the output to assume a high-impedance OFF-state. This device has the input-disable feature, which allows floating input signals. The inputs are disabled when the output enable input nOE is LOW.