74AUP1Z04

[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are  bserved.
[2] For SC-88 packages: above 87.5 the value of P_tot derates linearly with 4.0 mW/K.
For XSON6 packages: above 45 the value of P_tot derates linearly with 2.4 mW/K.

The 74AUP1Z04 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

The 74AUP1Z04 combines the functions of the 74AUP1GU04 and 74AUP1G04 with enable circuitry and an internal bias resistor to provide a device optimized for use in crystal oscillator applications.

The 74AUP1Z04 ensures a very low static and dynamic power consumption across the entire V_CC range from 0.8 V to 3.6 V.

The 74AUP1Z04 is fully specified for partial power-down applications using I_OFF at output Y. The I_OFF circuitry disables the output Y, preventing the damaging backflow current through the device when it is powered down.

When not in use the EN input of the 74AUP1Z04 can be driven HIGH, pulling up the X1 input and putting the device in a low power disable mode. Schmitt-trigger action at theEN input makes the circuit tolerant to slower input rise and fall times across the entire V_CC range from 0.8 V to 3.6 V.

The integration of the two devices into the 74AUP1Z04 produces the benefits of a compact footprint, lower power dissipation and stable operation over a wide range of frequency and temperature.