Features: · Wide supply voltage range from 2.3 V to 3.6 V· High noise immunity· ESD protection: *HBM JESD22-A114E Class 3A exceeds 5000 V *MM JESD22-A115-A exceeds 200 V *CDM JESD22-C101C exceeds 1000 V *Low static power consumption; ICC = 1.5 mA (maximum)· Latch-up performance exceeds 100 mA per ...
74AUP1T97: Features: · Wide supply voltage range from 2.3 V to 3.6 V· High noise immunity· ESD protection: *HBM JESD22-A114E Class 3A exceeds 5000 V *MM JESD22-A115-A exceeds 200 V *CDM JESD22-C101C exceeds 10...
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Symbol |
Parameter |
Conditions |
Min |
Max |
Unit |
VCC |
supply voltage |
-0.5 |
+4.6 |
V | |
IIK |
input clamping current | VI < 0 V |
-50 |
- |
mA |
VI |
input voltage | [1] |
-0.5 |
+4.6 |
V |
IOK |
output clamping current | VO > VCC or VO < 0 V |
-50 |
- |
mA |
VO |
output voltage | Active mode and Power-down mode [1] |
-0.5 |
+4.6 |
V |
IO |
output current | VO = 0 V to VCC |
- |
±20 |
mA |
ICC |
supply current |
- |
50 |
mA | |
IGND |
ground current |
-50 |
- |
mA | |
Tstg |
storage temperature |
-65 |
+150 |
||
Ptot |
total power dissipation | Tamb = -40 °C to +125 °C [2] |
- |
250 |
mW |
The 74AUP1T97 provides low-power, low-voltage configurable logic gate functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter and buffer. All inputs can be connected to VCC or GND.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V.
The 74AUP1T97 is designed for logic-level translation applications with input switching levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single 2.5 V or 3.3 V supply voltage.
The wide supply voltage range ensures normal operation as battery voltage drops from 3.6 V to 2.3 V.
The 74AUP1Z04 is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
Schmitt trigger inputs make the circuit of the 74AUP1Z04 tolerant to slower input rise and fall times across the entire VCC range.