74AUP1G97

Features:

· Wide supply voltage range from 0.8 V to 3.6 V
· High noise immunity
· ESD protection:
    * HBM JESD22-A114-D Class 3A exceeds 5000 V
    * MM JESD22-A115-A exceeds 200 V
    * CDM JESD22-C101-C exceeds 1000 V
· Low static power consumption; ICC = 0.9 mA (maximum)
· Latch-up performance exceeds 100 mA per JESD 78 Class II
· Inputs accept voltages up to 3.6 V
· Low noise overshoot and undershoot < 10 % of VCC
· IOFF circuitry provides partial Power-down mode operation
· Multiple package options
· Specified from -40 °C to +85 °C and -40 °C to +125 °C


Pinout




Specifications

Symbol	Parameter	Conditions	Min	Max	Unit
VCC	supply voltage		-0.5	+4.6	V
IIK	input clamping current	VI < 0 V	-	-50	mA
VI	input voltage	[1]	-0.5	+4.6	V
IOK	output clamping current	VO > VCC or VO < 0 V	-	±50	mA
VO	output voltage	Active mode and Power-down mode [1]	-0.5	+4.6	V
IO	output current	VO = 0 V to VCC	-	±20	mA
ICC	supply current		-	50	mA
IGND	ground current		-	-50	mA
Tstg	storage temperature		-65	+150
Ptot	total power dissipation	Tamb = -40 °C to +125 °C [2]	-	250	mW

Description

The 74AUP1G97 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

The 74AUP1G97 is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

The 74AUP1G97 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter and buffer. All inputs can be connected to VCC or GND.

Schmitt trigger action of the 74AUP1G97 at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

The inputs switch of the 74AUP1G97 at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.