Features: · Wide supply voltage range from 0.8 V to 3.6 V· High noise immunity· Complies with JEDEC standards:· JESD8-12 (0.8 V to 1.3 V)· JESD8-11 (0.9 V to 1.65 V)· JESD8-7 (1.2 V to 1.95 V)· JESD8-5 (1.8 V to 2.7 V)· JESD8-B (2.7 V to 3.6 V)· ESD protection:· HBM JESD22-A114-C exceeds 2000 V· M...
74AUP1G79: Features: · Wide supply voltage range from 0.8 V to 3.6 V· High noise immunity· Complies with JEDEC standards:· JESD8-12 (0.8 V to 1.3 V)· JESD8-11 (0.9 V to 1.65 V)· JESD8-7 (1.2 V to 1.95 V)· JESD...
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Symbol | Parameter | Min | Max | Unit |
IGND | ground current | - | -50 | mA |
Tstg | storage temperature | -65 | +150 | °C |
Ptot | total power dissipation Tamb = -40 °C to +125 °C |
- | 250 | mW |
The 74AUP1G79 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
The 74AUP1G79 ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
The 74AUP1G79 is fully specified for partial power-down applications using IOFF.
The IOFF circuitry of the 74AUP1G79 disables the output, preventing the damaging backflow current through the device when it is powered down.
The 74AUP1G79 provides the single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.