74AUP1G79

Features: · Wide supply voltage range from 0.8 V to 3.6 V· High noise immunity· Complies with JEDEC standards:· JESD8-12 (0.8 V to 1.3 V)· JESD8-11 (0.9 V to 1.65 V)· JESD8-7 (1.2 V to 1.95 V)· JESD8-5 (1.8 V to 2.7 V)· JESD8-B (2.7 V to 3.6 V)· ESD protection:· HBM JESD22-A114-C exceeds 2000 V· M...

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SeekIC No. : 004249537 Detail

74AUP1G79: Features: · Wide supply voltage range from 0.8 V to 3.6 V· High noise immunity· Complies with JEDEC standards:· JESD8-12 (0.8 V to 1.3 V)· JESD8-11 (0.9 V to 1.65 V)· JESD8-7 (1.2 V to 1.95 V)· JESD...

floor Price/Ceiling Price

Part Number:
74AUP1G79
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/3/10

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Product Details

Description



Features:

·  Wide supply voltage range from 0.8 V to 3.6 V
·  High noise immunity
·  Complies with JEDEC standards:
·  JESD8-12 (0.8 V to 1.3 V)
·  JESD8-11 (0.9 V to 1.65 V)
·  JESD8-7 (1.2 V to 1.95 V)
·  JESD8-5 (1.8 V to 2.7 V)
·  JESD8-B (2.7 V to 3.6 V)
·  ESD protection:
·  HBM JESD22-A114-C exceeds 2000 V
·  MM JESD22-A115-A exceeds 200 V
·  CDM JESD22-C101-C exceeds 1000 V
·  Low static power consumption; ICC = 0.9 mA (maximum)
·  Latch-up performance exceeds 100 mA per JESD 78 Class II
·  Inputs accept voltages up to 3.6 V
·  Low noise overshoot and undershoot < 10 % of VCC
·  IOFF circuitry provides partial Power-down mode operation
·  Multiple package options
·  Specified from -40 °C to +85 °C and -40 °C to +125 °C



Pinout

  Connection Diagram


Specifications

Symbol Parameter Min Max Unit
IGND ground current - -50 mA
Tstg storage temperature -65 +150 °C
Ptot total power
dissipation Tamb = -40 °C to +125 °C
- 250 mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP5 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.



Description

The 74AUP1G79 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

The 74AUP1G79 ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

The 74AUP1G79 is fully specified for partial power-down applications using IOFF.

The IOFF circuitry of the 74AUP1G79 disables the output, preventing the damaging backflow current through the device when it is powered down.

The 74AUP1G79 provides the single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.




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