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74AUP1G240

Features: `Wide supply voltage range from 0.8 Vto3.6V` High noise immunity `Complies with JEDEC standards: -JESD8-12 (0.8 Vto1.3 V)-JESD8-11 (0.9 Vto1.65V) -JESD8-7 (1.2 Vto1.95V) -JESD8-5 (1.8 Vto2.7V) -JESD8-B (2.7 Vto3.6V)` ESD protection: -HBM JESD22-A114-D exceeds 5000V -MM JESD22-A115-A e...

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SeekIC No. : 004249529 Detail

74AUP1G240: Features: `Wide supply voltage range from 0.8 Vto3.6V` High noise immunity `Complies with JEDEC standards: -JESD8-12 (0.8 Vto1.3 V)-JESD8-11 (0.9 Vto1.65V) -JESD8-7 (1.2 Vto1.95V) -JESD8-5 (1.8 Vt...

74AUP1G240 Data Sheet

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Part Number:
74AUP1G240
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

`Wide supply voltage range from 0.8 Vto3.6V
` High noise immunity
`Complies with JEDEC standards: 
   -JESD8-12 (0.8 Vto1.3 V) 
   -JESD8-11 (0.9 Vto1.65V)
   -JESD8-7 (1.2 Vto1.95V)
   -JESD8-5 (1.8 Vto2.7V)
   -JESD8-B (2.7 Vto3.6V)
` ESD protection:
   -HBM JESD22-A114-D exceeds 5000V
   -MM JESD22-A115-A exceeds 200V
   -CDM JESD22-C101-C exceeds 1000V
`Low static power consumption; ICC = 0.9A (maximum)
`Latch-up performance exceeds 100mA per JESD 78 Class II
`Inputs accept voltages up to 3.6V
`Low noise overshoot and undershoot < 10 % of VCC
`Input-disable feature allows ?oating input conditions


Pinout

Connection Diagram


Specifications

Symbol
Parameter
Conditions
Min
Max
Unit
VCC
IIK
VI
 supply voltage
input clamping current
input voltage
VI <0V
-0.5
-
[1] -0.5
+4.6
-50
+4.6
V
mA
V
IOK
VO
IO
 output clamping current
output voltage
output current		 VO >VCC or VO <0V
Active mode and Power-down mode
VO =0 V to VCC
-
[1] -0.5
-
±50
+4.6
±20
mA
V
mA
ICC
IGND
Tstg
 supply current
ground current
storage temperature		  
-
-
-65
50
-50
+150
mA
mA
Ptot
 total power dissipation Tamb =-40 to +125
[2] -
250
mW

[1]The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]For TSSOP5 packages: above 87.5 the value of Ptot  derates linearly with 4.0mW/K.
For XSON6 packages: above 45 the value of Ptot derates linearly with 2.4mW/K.


Description

The 74AUP1G240 is a high-performance, low-power, low-voltage, Si-gate CMOS device,superior to most advanced CMOS compatible TTL families.


Schmitt-trigger action at all inputs makes the circuit tolerant to slower input riseand fall times across the entire VCC  range from 0.8 V to 3.6 V.

The 74AUP1G240 ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

The 74AUP1G240 is fully specified for partial Power-down applications using IOFF
The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

The 74AUP1G240 provides the single inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE) . A HIGH level at pin OE causes the output to assume a high-impedance OFF-state.

The 74AUP1G240 has the input-disable feature, which allows floating input signals. The inputs are disabled when the output enable input OE is HIGH.




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