74ALVT16953

Features: • Two 8-bit registered transceivers• 5V I/O Compatible• 3-State buffers• Output capability: +64mA/32mA• TTL input and output switching levels• Input and output interface capability to systems at 5V supply• Bus hold data inputs eliminate the need ...

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SeekIC No. : 004249510 Detail

74ALVT16953: Features: • Two 8-bit registered transceivers• 5V I/O Compatible• 3-State buffers• Output capability: +64mA/32mA• TTL input and output switching levels• Input and...

floor Price/Ceiling Price

Part Number:
74ALVT16953
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/23

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Product Details

Description



Features:

• Two 8-bit registered transceivers
• 5V I/O Compatible
• 3-State buffers
• Output capability: +64mA/32mA
• TTL input and output switching levels
• Input and output interface capability to systems at 5V supply
• Bus hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
• Live insertion/extraction permitted
• Power-up 3-State
• Power-up reset
• No bus current loading when output is tied to 5V bus
• Latch-up protection exceeds 500mA per JEDEC Std 17
• ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model



Pinout

  Connection Diagram


Specifications

SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage   0.5 to 7.0 V
IIK DC input diode current VI < 0 18 mA
VI DC input voltage3   1.2 to +7.0 v
IOK DC output diode current VO < 0 50 mA
VOUT DC output voltage3 Output in Off or High state 0.5 to +5.5 v

IOUT
DC output current Output in Low state 128 mA
Output in High state 64
Tstg Storage temperature range   65 to +150 °C



Description

The 74ALVT16953 is a high-performance BiCMOS product designed for VCC operation at 2.5V or 3.3V with I/O compatibility up to 5V.

The 74ALVT16953 is a dual octal registered inverting transceiver.Two 8-bit registers store data flowing in both directions between two bidirectional buses. Data applied to the inputs is entered and stored on the rising edge of the Clock (nCPXX) provided that the Clock Enable (nCEXX) is Low. The data is then present at the 3-State output buffers, but is only accessible when the Output Enable (nOEXX) is Low. Data flow from A inputs to B outputs is the same as
for B inputs to A outputs.


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