74ALVT16373

Features: • 16-bit transparent latch• 5V I/O compatibile• 3-State buffers• Output capability: +64mA/-32mA• TTL input and output switching levels• Input and output interface capability to systems at 5V supply• Bus-hold data inputs eliminate the need for ext...

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74ALVT16373 Picture
SeekIC No. : 004249493 Detail

74ALVT16373: Features: • 16-bit transparent latch• 5V I/O compatibile• 3-State buffers• Output capability: +64mA/-32mA• TTL input and output switching levels• Input and output...

floor Price/Ceiling Price

Part Number:
74ALVT16373
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/21

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Product Details

Description



Features:

• 16-bit transparent latch
• 5V I/O compatibile
• 3-State buffers
• Output capability: +64mA/-32mA
• TTL input and output switching levels
• Input and output interface capability to systems at 5V supply
• Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
• Live insertion/extraction permitted
• Power-up reset
• Power-up 3-State
• No bus current loading when output is tied to 5V bus
• Latch-up protection exceeds 500mA per JEDEC Std 17
• ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model



Pinout

  Connection Diagram


Specifications

SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC
DC supply voltage   0.5 to +4.6 V
IIK
DC input diode current VI < 0
50 mA
VI
DC input voltage3
  0.5 to +7.0 V
IOK
DC output diode current VO < 0
50 mA
VOUT

DC output voltage3
Output in Off or High state 0.5 to +7.0 V
IOUT
DC toutput current Output in Low state 128 mA
Output in High state 64
Tstg
Storage temperature range   65 to +150
°C



Description

The 74ALVT16373 is a high-performance BiCMOS product designed for VCC operation at 2.5V or 3.3V with I/O compatibility up to 5V.

The 74ALVT16373 is a 16-bit transparent D-type latch with non-inverting 3-State bus compatible outputs. The device can be used as two 8-bit latches or one 16-bit latch. When latch enable (LE) input is High, the Q outputs follow the data (D) inputs. When latch enable is taken Low, the Q outputs are latched at the levels of the D inputs one setup time prior to the High-to-Low transition.


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