Features: • ESD protection exceeds 2000V per Mil-Std-883C, Method 3015; exceeds 200V using machine model• Latch-up protection exceeds 500mA per JEDEC Standard JESD-17.• Distributed VCC and GND pin configuration minimizes high-speed switching noise.• Output capability (32mA ...
74ALVT16260: Features: • ESD protection exceeds 2000V per Mil-Std-883C, Method 3015; exceeds 200V using machine model• Latch-up protection exceeds 500mA per JEDEC Standard JESD-17.• Distributed...
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Buffers & Line Drivers 16-Bit Buffer/Driver With 3-State Outputs
SYMBOL | PARAMETER | CONDITIONS | RATING | UNIT |
VCC | DC supply voltage | 0.5 to +4.6 | V | |
IIK | DC input diode current | VI < 0 | 50 | mA |
VI | DC input voltage3 | -0.5 to +7.0 | V | |
IOK | DC output diode current | VO < 0 | 50 | mA |
VOUT | DC output voltage3 | Output in Off or High state | -0.5 to +7.0 | V |
IOUT | DC output current |
output in Low state |
128 |
mA |
output in High state | -64 | |||
Tstg | Storage temperature range | -65 to 150 | °C |
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
Three 12-bit I/O ports (A1A12, 1B11B12, and 2B12B12) of the 74ALVT16260 are available for address and/or data transfer. The output enable (OE1B, OE2B, and OEA) inputs control the bus transceiver functions. The OE1B and OE2B control signals also allow bank control in the A to B direction.
Address and/or data information of the 74ALVT16260 can be stored using the internal storage latches. The latch enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch enable input is high, the latch is transparent. When the latch enable input goes low, the data present at the inputs is latched and remains latched until the latch enable input is returned high.
To ensure the high-impedance state of the 74ALVT16260 during power-up or power-down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current sinking capability of the driver.
The 74ALVT16260 is available in a 56-pin Shrink Small Outline Package (SSOP) and 56-pin Thin Shrink Small Outline Package (TSSOP).