74ALVCH32501

The 74ALVCH32501 is a high-performance CMOS  product designed for V_CC operation at 2.5 and 3.3 V with I/O compatibility up to 5 V.

Active bus-hold circuitry of the 74ALVCH32501 is provided to hold unused or floating data inputs at a valid logic level. The 74ALVCH32501 can be used as two 18-bit transceivers or one 36-bit transceiver featuring n on-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OE_AB and OE_BA), latch enable (LE_AB and LE_BA), and clock inputs (CP_AB and CP_BA). For A-to-B data flow, the 74ALVCH32501 operates in the transparent mode when LE_AB is HIGH. When input LE_AB of the 74ALVCH32501 is LOW, the A data is latched if input CP_AB is held at a HIGH or LOW level. If input LE_AB is LOW, the A data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CP_AB. When input OE_AB is HIGH, the outputs are active. When input OE_AB is LOW, the outputs are in the high-impedance state.

Data of the 74ALVCH32501 flow for B-to-A is similar to that of A-to-B, but uses inputs OE_BA, LE_BA and CP_BA. The output enables are complimentary (OE_AB is active HIGH, and OE_BA is active LOW).

To ensure the high-impedance state of the 74ALVCH32501 during power-up or power-down, pin OEBA should be tied to VCC through a  a pull-down resistor. The minimum value of the resistor is determined by the current-sinking or current-sourcing capability of the driver.