Features: · 3-state non-inverting outputs for bus oriented applications· Wide supply voltage range of 1.2 to 3.6 V· Complies with JEDEC standard no. 8-1A· Current drive ±24 mA at 3.0 V· Universal bus transceiver with D-type latches and D-type flip-flops capable of operating in transparent, latched...
74ALVCH32501: Features: · 3-state non-inverting outputs for bus oriented applications· Wide supply voltage range of 1.2 to 3.6 V· Complies with JEDEC standard no. 8-1A· Current drive ±24 mA at 3.0 V· Universal bu...
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Buffers & Line Drivers 16-Bit Buffer/Driver With 3-State Outputs
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
MAX. |
UNIT |
VCC |
DC supply voltage |
-0.5 |
+4.6 |
V | |
VI |
DC input voltage |
for control pins; note 1 |
-0.5 |
+4.6 |
V |
for data input pins; note 1 |
-0.5 |
VCC + 0.5 |
V | ||
IIK |
DC input diode current |
VI < 0 |
-50 |
mA | |
IOK |
DC output clamping diode current |
VO < 0; note 1 |
50 |
mA | |
VO |
DC output voltage |
see note 1 |
-0.5 |
VCC + 0.5 |
V |
IO |
DC output sink current |
VO = 0 to VCC |
-50 |
mA | |
ICC, IGND |
DC VCC or GND current |
±100 |
mA | ||
Tstg |
storage temperature |
-65 |
+150 |
mA | |
PD |
power dissipation per packages |
for temperature range: -40 to +85 °C; note 2 |
1000 |
mW |
The 74ALVCH32501 is a high-performance CMOS product designed for VCC operation at 2.5 and 3.3 V with I/O compatibility up to 5 V.
Active bus-hold circuitry of the 74ALVCH32501 is provided to hold unused or floating data inputs at a valid logic level. The 74ALVCH32501 can be used as two 18-bit transceivers or one 36-bit transceiver featuring n on-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock inputs (CPAB and CPBA). For A-to-B data flow, the 74ALVCH32501 operates in the transparent mode when LEAB is HIGH. When input LEAB of the 74ALVCH32501 is LOW, the A data is latched if input CPAB is held at a HIGH or LOW level. If input LEAB is LOW, the A data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When input OEAB is HIGH, the outputs are active. When input OEAB is LOW, the outputs are in the high-impedance state.
Data of the 74ALVCH32501 flow for B-to-A is similar to that of A-to-B, but uses inputs OEBA, LEBA and CPBA. The output enables are complimentary (OEAB is active HIGH, and OEBA is active LOW).
To ensure the high-impedance state of the 74ALVCH32501 during power-up or power-down, pin OEBA should be tied to VCC through a a pull-down resistor. The minimum value of the resistor is determined by the current-sinking or current-sourcing capability of the driver.