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74ALVCH16952

Features: • Complies with JEDEC standard no. 8-1A• CMOS low power consumption• MULTIBYTETM flow-through pin-out architecture• Low inductance, multiple center power and ground pins for minimum noise and ground bounce• Direct interface with TTL levels• Output driv...

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74ALVCH16952: Features: • Complies with JEDEC standard no. 8-1A• CMOS low power consumption• MULTIBYTETM flow-through pin-out architecture• Low inductance, multiple center power and ground...

74ALVCH16952 Data Sheet

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Part Number:
74ALVCH16952
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Complies with JEDEC standard no. 8-1A
• CMOS low power consumption
• MULTIBYTETM flow-through pin-out architecture
• Low inductance, multiple center power and ground pins for minimum noise and ground bounce
• Direct interface with TTL levels
• Output drive capability 50W transmission lines @ 85°C


Pinout

Connection Diagram


Specifications

SYMBOL
 PARAMETER CONDITIONS
RATING
UNIT
VCC
 DC supply voltage  
0.5 to +4.6
V
IIK
 DC input diode current VI<0
-50
mA
VI
 DC input voltage For control pins1
0.5 to +4.6
V
For data inputs1
0.5 to VCC +0.5
IOK
 DC output diode current VO>VCC or VO<0
±50
mA
VO
 DC output voltage Note 1
-50toVcc+0.5
V
IO
 DC output source or sink current VO = 0 to VCC
±50
mA
IGND, ICC
 DC VCC or GND current  
±100
mA
Tstg
 Storage temperature range  
-65to+150
PTOT
 Power dissipation per package
plastic medium-shrink (SSOP)
plastic thin-medium-shrink (TSSOP)		 For temperature range: 40 to +125 °C
above +55°C derate linearly with 11.3 mW/
above +55°C derate linearly with 8 mW/K
850
600
m/W



Description

The 74ALVCH16952 consists of two sections, each containing a dual octal non-inverting registered transceiver. Two 8-bit back to back registers store data flowing in both directions between two bi-directional busses. Data applied to the inputs is entered and stored on the rising edge of the clock (CPXX, where X is AB or BA) provided that the clock enable (CEXX) is LOW. The data of the 74ALVCH16952 is then present at the 3-State output buffers, but is only accessible when the output enable input (OEXX) is LOW. Data flow from A inputs to B outputs is the same as for B inputs to A outputs.




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