74ALVCH16843

Features:

• Wide supply voltage range of 1.2V to 3.6V
• Complies with JEDEC standard no. 8-1A.
• CMOS low power consumption
• Direct interface with TTL levels
• Current drive ± 24 mA at 3.0 V
• MULTIBYTETM flow-through standard pin-out architecture
• Low inductance multiple V_CC and GND pins for minimum noise and ground bounce
• All data inputs have bus hold
• Output drive capability 50W transmission lines @ 85°C


Pinout




Specifications

SYMBOL	PARAMETER	CONDITIONS	RATING	UNIT
VCC	DC supply voltage		0.5 to +4.6	V
IIK	DC input diode current	VI < 0	50	mA
IOK	DC output diode current	VO > VCC or VO < 0	±50	mA
VO	DC output voltage	note 2	0.5 to VCC +0.5	V
IO	DC output source or sink current	VO = 0 to VCC	±50	mA
ICC, IGND	DC VCC or GND current		±100	mA
Tstg	storage temperature range		65 to +150	°C
Ptot	power dissipationper package plastic medium-shrink (SSOP) plastic thin-medium-shrink (TSSOP)	for temperature range: -40 to +125 °C above +55°C derate linearly with 11.3 mW/K above +55°C derate linearly with 8 mW/K	850 600	mW
VI	DC input voltage	For control pins2	0.5 to +4.6	V
		For data inputs2	0.5 to VCC +0.5

 


Description

The 74ALVCH16843 has two 9bit D-type latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. The two sections of each register are controlled independently by the latch enable (nLE), clear (n CLR),preset (nPRE) and output enable (nOE) control gates.

When nOE is LOW, the data of the 74ALVCH16843 in the registers appear at the outputs.When nOE is HIGH, the outputs are in the high impedance OFF state. Operation of the nOE input does not affect the state of the flip-flops.