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74ALVCH16825

Features: • Wide supply voltage range of 1.2V to 3.6V• Complies with JEDEC standard no. 8-1A.• CMOS low power consumption• Direct interface with TTL levels• Current drive ± 24 mA at 3.0 V• MULTIBYTETM flow-through standard pin-out architecture• Low inducta...

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SeekIC No. : 004249446 Detail

74ALVCH16825: Features: • Wide supply voltage range of 1.2V to 3.6V• Complies with JEDEC standard no. 8-1A.• CMOS low power consumption• Direct interface with TTL levels• Current dri...

74ALVCH16825 Data Sheet

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Part Number:
74ALVCH16825
Supply Ability:
5000

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  • 1~5000
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  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Wide supply voltage range of 1.2V to 3.6V
• Complies with JEDEC standard no. 8-1A.
• CMOS low power consumption
• Direct interface with TTL levels
• Current drive ± 24 mA at 3.0 V
• MULTIBYTETM flow-through standard pin-out architecture
• Low inductance multiple VCC and GND pins for minimum noise and ground bounce
• All data inputs have bus hold
• Output drive capability 50W transmission lines @ 85°C


Pinout

Connection Diagram


Specifications

SYMBOL
 PARAMETER CONDITIONS
RATING
UNIT
VCC
 DC supply voltage  
0.5 to +4.6
V
IIK
 DC input diode current VI<0
-50
mA
VI
 DC input voltage For control pins1
0.5 to +4.6
V
For data inputs1
0.5 to VCC +0.5
IOK
 DC output diode current VO>VCC or VO<0
±50
mA
VO
 DC output voltage Note 1
-50toVcc+0.5
V
IO
 DC output source or sink current VO = 0 to VCC
±50
mA
IGND, ICC
 DC VCC or GND current  
±100
mA
Tstg
 Storage temperature range  
-65to+150
PTOT
 Power dissipation per package
plastic medium-shrink (SSOP)
plastic thin-medium-shrink (TSSOP)		 For temperature range: 40 to +125 °C
above +55°C derate linearly with 11.3 mW/K
above +55°C derate linearly with 8 mW/K
850
600
m/W



Description

The 74ALVCH16825 is an 18bit non-inverting buffer/driver with 3-State outputs for bus-oriented applications.

The 74ALVCH16825 consists of two 9-bit sections with separate output enable signals. For either 9-bit buffer section, the two output enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be LOW for corresponding D outputs to be active. If either output enable input is HIGH, the outputs of that 9-buffer section are in the
high impedance state.

The 74ALVCH16825 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.




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