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74ALVCH16821

Features: • Wide supply voltage range of 1.2V to 3.6V• Complies with JEDEC standard no. 8-1A• Current drive ± 24 mA at 3.0 V• CMOS low power consumption• Direct interface with TTL levels• MULTIBYTETM flow-through standard pin-out architecture• Low inductan...

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74ALVCH16821: Features: • Wide supply voltage range of 1.2V to 3.6V• Complies with JEDEC standard no. 8-1A• Current drive ± 24 mA at 3.0 V• CMOS low power consumption• Direct interfa...

74ALVCH16821 Data Sheet

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Part Number:
74ALVCH16821
Supply Ability:
5000

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Product Details

Description



Features:

• Wide supply voltage range of 1.2V to 3.6V
• Complies with JEDEC standard no. 8-1A
• Current drive ± 24 mA at 3.0 V
• CMOS low power consumption
• Direct interface with TTL levels
• MULTIBYTETM flow-through standard pin-out architecture
• Low inductance multiple VCC and ground pins for minimum noise and ground bounce
• All data inputs have bus hold
• Output drive capability 50W transmission lines @ 85°C


Pinout

Connection Diagram


Specifications

SYMBOL
 PARAMETER CONDITIONS
RATING
UNIT
VCC
 DC supply voltage  
0.5 to +4.6
V
IIK
 DC input diode current VI<0
-50
mA
VI
 DC input voltage For control pins1
0.5 to +4.6
V
For data inputs1
0.5 to VCC +0.5
IOK
 DC output diode current VO>VCC or VO<0
±50
mA
VO
 DC output voltage Note 1
-50toVcc+0.5
V
IO
 DC output source or sink current VO = 0 to VCC
±50
mA
IGND, ICC
 DC VCC or GND current  
±100
mA
Tstg
 Storage temperature range  
-65to+150
PTOT
 Power dissipation per package
plastic medium-shrink (SSOP)
plastic thin-medium-shrink (TSSOP)		 For temperature range: 40 to +125 °C
above +55°C derate linearly with 11.3 mW/
above +55°C derate linearly with 8 mW/K
850
600
m/W



Description

The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates.

Each register of the 74ALVCH16821 is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop's Q output.

When nOE is LOW, the data of the 74ALVCH16821 in the register appears at the outputs. When nOE is HIGH, the outputs are in high impedance OFF state. Operation of the nOE input does not affect the state of the flip-flops.

The 74ALVCH16821 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.




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