74ALVCH16652

The 74ALVCH16652 consists of 16 non-inverting bus transceiver circuits with 3-state outputs, D-type flip-flopsand control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internalstorage registers.

Data of the 74ALVCH16652 on the 'A' or 'B', or both buses, will be stored in the internal registers, at the appropriate clock inputs (nCP_AB or nCP_BA) regardless of the select inputs (nS_AB and nS_BA) or output enable (nOE_AB and nOE_BA) control inputs.

Depending on the select inputs nSAB and nSBA data can directly go from input to output (real-time mode) or data can be controlled by the clock (storage mode), when OE inputs permit this operating mode.

The output of the 74ALVCH16652 enable inputs nOE_AB and nOE_BA determine the  operation mode of the transceiver. When nOEAB is LOW,no data transmission from nBn to nAn is possible and when nOE_BA is HIGH, no data transmission from nBn to nAn is possible.

When nSAB and nSBA of the 74ALVCH16652 are in the real-time transfer mode, it is also possible to store data without using the internalD-type flip-flops by simultaneously enabling nOEAB and nOE_BA. In this configuration each output reinforces its input.

Active bus hold circuitry of the 74ALVCH16652 is provided to hold unused or floating data inputs at a valid logic level.