74ALVCH16646

The 74ALVCH16646 consists of 16 non-inverting bus transceiver circuits with 3-State outputs, D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the internal registers. Data on the 'A' or 'B' bus will be clocked in the internal registers, as the appropriate clock (CP_AB or CP_BA) goes to a HIGH logic level. Output of the 74ALVCH16646 enable (OE) and direction (DIR) inputs are provided to control the transceiver function. In the  ansceiver mode, data present at the high-impedance port may be stored in either the 'A' or 'B' register, or in both. The select source inputs (SAB and SBA) can multiplex stored and real-time (transparent mode) data. Thedirection (DIR) input determines which bus will receive data when OE is active (LOW). In the isolation mode (OE = HIGH), 'A' data may be stored in the 'B' register and/or 'B' data may be stored in the 'A' register.

When an output function of the 74ALVCH16646 is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, 'A' or 'B' may be driven at a time.

To ensure the high impedance state of the 74ALVCH16646 during power up or power down, OE should be tied to V_CC through a pullup resistor; theminimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.

Active bus-hold circuitry of the 74ALVCH16646 is provided to hold unused or floating data inputs at a valid logic level.