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74ALVCH162827

Features: • Complies with JEDEC standard no. 8-1A.• CMOS low power consumption• Direct interface with TTL levels• Current drive ± 12 mA at 3.0 V• MULTIBYTETM flow-through standard pin-out architecture• Low inductance multiple VCC and GND pins for minimum noise a...

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SeekIC No. : 004249430 Detail

74ALVCH162827: Features: • Complies with JEDEC standard no. 8-1A.• CMOS low power consumption• Direct interface with TTL levels• Current drive ± 12 mA at 3.0 V• MULTIBYTETM flow-throu...

74ALVCH162827 Data Sheet

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Part Number:
74ALVCH162827
Supply Ability:
5000

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Product Details

Description



Features:

• Complies with JEDEC standard no. 8-1A.
• CMOS low power consumption
• Direct interface with TTL levels
• Current drive ± 12 mA at 3.0 V
• MULTIBYTETM flow-through standard pin-out architecture
• Low inductance multiple VCC and GND pins for minimum noise and ground bounce
• Integrated 30  termination resistors


Pinout

Connection Diagram


Specifications

SYMBOL
 PARAMETER CONDITIONS
RATING
UNIT
VCC
 DC supply voltage  
0.5 to +4.6
V
IIK
 DC input diode current VI<0
-50
mA
VI
 DC input voltage For control pins1
0.5 to +4.6
V
For data inputs1
0.5 to VCC +0.5
IOK
 DC output diode current VO>VCC or VO<0
±50
mA
VO
 DC output voltage Note 1
-50toVcc+0.5
V
IO
 DC output source or sink current VO = 0 to VCC
±50
mA
IGND, ICC
 DC VCC or GND current  
±100
mA
Tstg
 Storage temperature range  
-65to+150
PTOT
 Power dissipation per package
plastic thin-medium-shrink (TSSOP)		 For temperature range: 40 to +125 °C
above +55°C derate linearly with 8 mW/K
600
m/W



Description

The 74ALVCH162827 high-performance CMOS device combines low static and dynamic power dissipation with high speed and high output drive.

The 74ALVCH162827 20-bit buffers provide high performance bus interface buffering for wide data/address paths or buses carrying parity. They have NAND Output Enables (nOE1, nOE2) for maximum control flexibility.

The 74ALVCH162827 is designed with 30W series resistance in both the pull-up and pull-down output structures. This design reduces line noise in applications such as memory address drivers, clock drivers and bus receivers/transmitters.

To ensure the high impedance state of the 74ALVCH162827 during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.

Active bus-hold circuitry of the 74ALVCH162827 is provided to hold unused or floating data inputs at a valid logic level.




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