74ALVCF162835

· Compatible with PC133 DIMM module specifications
· 1.65V to 3.6V V_CC supply operation
· 3.6V tolerant outputs
·26Ω series resistors in outputs
· t_{PD(CLK to On)}
  3.7 ns max for 3.0V to 3.6V V_CC
  4.6 ns max for 2.3V to 2.7V V_CC
  7.4 ns max for 1.65V to 1.95V V_CC
· Power-down high impedance outputs
· Latchup conforms to JEDEC JED78
· ESD performance:
  Human body model > 2000V
  Machine model > 200V

Supply Voltage (V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . -0.5V to +4.6V
DC Input Voltage (V_I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . -0.5V to +4.6V
Output Voltage (V_O)
Outputs 3-STATE . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V
Outputs Active (Note 4) . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . -0.5V to V_CC + 0.5V
DC Input Diode Current (IIK)
VI < 0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA
DC Output Diode Current (I_OK)
VO < 0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . .. . . . . . . . .-50 mA
VO > V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +50 mA
DC Output Source/Sink Current (IOL/IOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
DC V_CC or Ground Current per . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .±100 mA
Supply Pin (I_CC or Ground)
Storage Temperature Range (Tstg) . . . . . . . . . . . . . . . . . . . . . . . .  . . .-65°C to +150°C

The 74ALVCF162835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes.
Data flow is controlled by output-enable (OE), latch-enable (LE), and clock (CLK) inputs. The device operates in Transparent Mode when LE is held HIGH. The device
operates in clocked mode when LE is LOW and CLK is toggled. Data of the 74ALVCF162835 transfers from the Inputs (In) to Outputs (On) on a Positive Edge Transition of the Clock. When OE is LOW, the output data is enabled. When OE is HIGH the output port is in a high impedance state.

The 74ALVCF162835 is designed with 26Ω series resistors in the outputs. This design reduces noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters.

The 74ALVCF162835 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O capability up to 3.6V.

The 74ALVCF162835 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.