74ALVC74

Features: · Wide supply voltage range from 1.65 to 3.6 V· Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V).· 3.6 V tolerant inputs/outputs· CMOS low power consumption· Direct interface with TTL levels (2.7 to 3.6 V)· Power-down mode· Latch-...

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74ALVC74 Picture
SeekIC No. : 004249399 Detail

74ALVC74: Features: · Wide supply voltage range from 1.65 to 3.6 V· Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V).· 3.6 V tolerant inputs/outputs· ...

floor Price/Ceiling Price

Part Number:
74ALVC74
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/31

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Product Details

Description



Features:

· Wide supply voltage range from 1.65 to 3.6 V
· Complies with JEDEC standard:
  JESD8-7 (1.65 to 1.95 V)
  JESD8-5 (2.3 to 2.7 V)
  JESD8B/JESD36 (2.7 to 3.6 V).
· 3.6 V tolerant inputs/outputs
· CMOS low power consumption
· Direct interface with TTL levels (2.7 to 3.6 V)
· Power-down mode
· Latch-up performance exceeds 250 mA
· ESD protection:
  HBM EIA/JESD22-A114-A exceeds 2000 V
  MM EIA/JESD22-A115-A exceeds 200 V.



Pinout

  Connection Diagram


Description

The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs.

The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs of the 74ALVC74 must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.




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