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74ALVC574

Features: · Wide supply voltage range from 1.65 to 3.6 V· Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V).· 3.6 V tolerant inputs/outputs· CMOS low power consumption· Direct interface with TTL levels (2.7 to 3.6 V)· Power-down mode· Latch-...

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SeekIC No. : 004249398 Detail

74ALVC574: Features: · Wide supply voltage range from 1.65 to 3.6 V· Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V).· 3.6 V tolerant inputs/outputs· ...

74ALVC574 Data Sheet

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Part Number:
74ALVC574
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

· Wide supply voltage range from 1.65 to 3.6 V
· Complies with JEDEC standard:
    JESD8-7 (1.65 to 1.95 V)
    JESD8-5 (2.3 to 2.7 V)
    JESD8B/JESD36 (2.7 to 3.6 V).
· 3.6 V tolerant inputs/outputs
· CMOS low power consumption
· Direct interface with TTL levels (2.7 to 3.6 V)
· Power-down mode
· Latch-up performance exceeds £250 mA
· ESD protection:
    2000 V Human Body Model (JESD22-A114-A)
    200 V Machine Model (JESD22-A115-A).


Pinout

Connection Diagram


Specifications

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage   -0.5 +4.6 V
IIK input diode current VI < 0 - -50 mA
VI input voltage   -0.5 +4.6 V
IOK output diode current VO > VCC or VO < 0 - ±50 mA
VO output voltage enable mode; notes 1 and 2 -0.5 VCC + 0.5 V
disable mode -0.5 +4.6 V
Power-down mode; note 2 -0.5 +4.6 V
IO output diode current VO = 0 to VCC - ±50 mA
IGND, ICC VCC or GND current   - ±100 mA
Tstg storage temperature   -65 +150
Ptot

power dissipation per package

    SO package



    TSSOP package

 

above 70 derate linearly with8 mW/K


above 60 derate linearly with 5.5 mW/K

-

 

-

500

 

500

mW

 

mW




Description

The 74ALVC574 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.

The 74ALVC574 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock (CP) input and an output enable (OE) input are common to allflip-flops.

The eight flip-flops of the 74ALVC574 will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition.

When OE is LOW, the contents of the eight flip-flops of the 74ALVC574 is available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.

The '574' is functionally identical to the '374', but the '374' has a different pin arrangement.




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