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74ALVC573

Features: · Wide supply voltage range from 1.65 to 3.6 V· Complies with JEDEC standards: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V).· 3.6 V tolerant inputs and outputs· CMOS low power consumption· Direct interface with TTL levels (2.7 to 3.6 V)· Power-down mode· L...

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SeekIC No. : 004249397 Detail

74ALVC573: Features: · Wide supply voltage range from 1.65 to 3.6 V· Complies with JEDEC standards: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V).· 3.6 V tolerant inputs and outp...

74ALVC573 Data Sheet

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Part Number:
74ALVC573
Supply Ability:
5000

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  • 1~5000
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  • 15 Days
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Product Details

Description



Features:

· Wide supply voltage range from 1.65 to 3.6 V
· Complies with JEDEC standards:
    JESD8-7 (1.65 to 1.95 V)
    JESD8-5 (2.3 to 2.7 V)
    JESD8B/JESD36 (2.7 to 3.6 V).
· 3.6 V tolerant inputs and outputs
· CMOS low power consumption
· Direct interface with TTL levels (2.7 to 3.6 V)
· Power-down mode
· Latch-up performance exceeds 250 mA
· ESD protection:
    HBM EIA/JESD22-A114-A exceeds 2000 V
    MM EIA/JESD22-A115-A exceeds 200 V.


Application

Connection Diagram


Specifications

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage   -0.5 +4.6 V
IIK input diode current VI < 0 - -50 mA
VI input voltage   -0.5 +4.6 V
IOK output diode current VO > VCC or VO < 0 - ±50 mA
VO output voltage enable mode; notes 1 and 2 -0.5 VCC + 0.5 V
disable mode -0.5 +4.6 V
Power-down mode; note 2 -0.5 +4.6 V
IO output source or sink current VO = 0 to VCC - ±50 mA
ICC, IGND VCC or GND current   - ±100 mA
Tstg storage temperature   -65 +150
Ptot power dissipation Tamb = -40 to +85; note 3 - 500 mW



Description

The 74ALVC573 is a high-performance, low-power,low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.

The 74ALVC573 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all internal latches.

The 74ALVC573 consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D-input changes.

When LE of the 74ALVC573 is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs.When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches.

The 74ALVC573 is functionally identical to the 74ALVC373, but the has a different pin arrangement.




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