Features: · Compatible with PC100 and PC133 DIMM module specifications· 1.65V to 3.6V VCC supply operation· 3.6V tolerant inputs and outputs· tPD (CLK to On) 3.5 ns max for 3.0V to 3.6V VCC 4.5 ns max for 2.3V to 2.7V VCC 8.0 ns max for 1.65V to 1.95V VCC· Power-off high impedance inputs and outpu...
74ALVC16838: Features: · Compatible with PC100 and PC133 DIMM module specifications· 1.65V to 3.6V VCC supply operation· 3.6V tolerant inputs and outputs· tPD (CLK to On) 3.5 ns max for 3.0V to 3.6V VCC 4.5 ns m...
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Buffers & Line Drivers 16-Bit Buffer/Driver With 3-State Outputs
Supply Voltage (VCC) −0.5V to +4.6V
DC Input Voltage (VI) −0.5V to 4.6V
Output Voltage (VO) (Note 2) −0.5V to VCC +0.5V
DC Input Diode Current (IIK)
VI < 0V −50 mA
DC Output Diode Current (IOK)
VO < 0V −50 mA
DC Output Source/Sink Current
(IOH/IOL) ±50 mA
DC VCC or GND Current per
Supply Pin (ICC or GND) ±100 mA
Storage Temperature Range (TSTG) −65°C to +150°C
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation.
Note 2: IO Absolute Maximum Rating must be observed.
The 74ALVC16838 contains sixteen non-inverting selectable buffered or registered paths. The device can be configured to operate in a registered, or flow through buffer mode by utilizing the register enable (REGE) and Clock (CLK) signals. The 74ALVC16838 operates in a 16-bit word wide mode. All outputs can be placed into 3-State through use of the OE Pin. These devices are ideally suited for buffered or registered 168 pin and 200 pin SDRAM DIMM memory modules.
The 74ALVC16838 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O compatibility up to 3.6V. The 74ALVC16838 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.