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74ALVC16836ADGG

Features: Wide supply voltage range of 1.2 V to 3.6 V Complies with JEDEC standard no. 8-1A. CMOS low power consumption Direct interface with TTL levels Current drive ±24 mA at 3.0 V MULTIBYTE TMflow-through standard pin-out architecture Low inductance multiple VCC and GND pins for minimum noise ...

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74ALVC16836ADGG: Features: Wide supply voltage range of 1.2 V to 3.6 V Complies with JEDEC standard no. 8-1A. CMOS low power consumption Direct interface with TTL levels Current drive ±24 mA at 3.0 V MULTIBYTE TMfl...

74ALVC16836ADGG Data Sheet

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Part Number:
74ALVC16836ADGG
Supply Ability:
5000

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  • 1~5000
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  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

  Wide supply voltage range of 1.2 V to 3.6 V
  Complies with JEDEC standard no. 8-1A.
  CMOS low power consumption
  Direct interface with TTL levels
  Current drive ±24 mA at 3.0 V
  MULTIBYTE TM flow-through standard pin-out architecture
  Low inductance multiple VCC and GND pins for minimum noise
     and ground bounce
  Output drive capability 50 Ω transmission lines @ 85°C
  Input diodes to accommodate strong drivers


Pinout

Connection Diagram


Description

The 74ALVC16836ADGG is a 20-bit universal bus driver. Data flow is controlled by active low output enable (OE ), active low latch enable(LE ) and clock inputs (CP).

When LE of the 74ALVC16836ADGG is LOW, the A to Y data flow is transparent. When LE isHIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP the A-data is stored in the latch/flip-flop.

When OE of the 74ALVC16836ADGG is LOW the outputs are active. When OE  is HIGH, theoutputs go to the high impedance OFF-state. Operation of the OE  input does not affect the state of the latch/flip-flop.

To ensure the high-impedance state during power up or power down, OE  should be tied to VCC  through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.




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