Position: Home  > All Categories> Integrated Circuits (ICs) > 74ALVC16836ADGG

74ALVC16836ADGG

Features: Wide supply voltage range of 1.2 V to 3.6 V Complies with JEDEC standard no. 8-1A. CMOS low power consumption Direct interface with TTL levels Current drive ±24 mA at 3.0 V MULTIBYTE TMflow-through standard pin-out architecture Low inductance multiple VCC and GND pins for minimum noise ...

product image

74ALVC16836ADGG Picture
See larger image
SeekIC No. : 004249385 Detail

74ALVC16836ADGG: Features: Wide supply voltage range of 1.2 V to 3.6 V Complies with JEDEC standard no. 8-1A. CMOS low power consumption Direct interface with TTL levels Current drive ±24 mA at 3.0 V MULTIBYTE TMfl...

74ALVC16836ADGG Data Sheet

floor Price/Ceiling Price

Get Latest Price
Part Number:
74ALVC16836ADGG
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

SeekIC Buyer Protection PLUS - newly updated for 2013!

  • Escrow Protection.
  • Guaranteed refunds.
  • Secure payments.
  • Learn more >>

Month Sales

268 Transactions

Rating

evaluate  (4.8 stars)

Upload time: 2024/11/21

add to my favourite

Payment Methods

All payment methods are secure and covered by SeekIC Buyer Protection PLUS.

Notice: When you place an order, your payment is made to SeekIC and not to your seller. SeekIC only pays the seller after confirming you have received your order. We will also never share your payment details with your seller.
Product Details

Description



Features:

  Wide supply voltage range of 1.2 V to 3.6 V
  Complies with JEDEC standard no. 8-1A.
  CMOS low power consumption
  Direct interface with TTL levels
  Current drive ±24 mA at 3.0 V
  MULTIBYTE TM flow-through standard pin-out architecture
  Low inductance multiple VCC and GND pins for minimum noise
     and ground bounce
  Output drive capability 50 Ω transmission lines @ 85°C
  Input diodes to accommodate strong drivers


Pinout

Connection Diagram


Description

The 74ALVC16836ADGG is a 20-bit universal bus driver. Data flow is controlled by active low output enable (OE ), active low latch enable(LE ) and clock inputs (CP).

When LE of the 74ALVC16836ADGG is LOW, the A to Y data flow is transparent. When LE isHIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP the A-data is stored in the latch/flip-flop.

When OE of the 74ALVC16836ADGG is LOW the outputs are active. When OE  is HIGH, theoutputs go to the high impedance OFF-state. Operation of the OE  input does not affect the state of the latch/flip-flop.

To ensure the high-impedance state during power up or power down, OE  should be tied to VCC  through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.




Customers Who Bought This Item Also Bought

Margin,quality,low-cost products with low minimum orders. Secure your online payments with SeekIC Buyer Protection.
You may also be interested in :
Motors, Solenoids, Driver Boards/Modules
IHSS57-36-20
ASD-B2-1521-B
Discrete Semiconductor Products
T508N12TOF
MUR20040
Optoelectronics
SFH7770
TLP423J
Test Equipment
TOP853
TOP2005
Relays
WIMA MKP4 0.22UF 630V
WIMA MKP4 4.7UF 630VDC
Cables, Wires - Management
NM-SF50+
CCK26.5-MM-190-30
View more