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74ALVC125

Features: · Wide supply voltage range from 1.65 to 3.6 V· Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V)· 3.6 V tolerant inputs/outputs· CMOS low power consumption· Direct interface with TTL levels (2.7 to 3.6 V)· Power-down mode· Latch-u...

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74ALVC125: Features: · Wide supply voltage range from 1.65 to 3.6 V· Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V)· 3.6 V tolerant inputs/outputs· C...

74ALVC125 Data Sheet

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Part Number:
74ALVC125
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

· Wide supply voltage range from 1.65 to 3.6 V
· Complies with JEDEC standard:
  JESD8-7 (1.65 to 1.95 V)
  JESD8-5 (2.3 to 2.7 V)
  JESD8B/JESD36 (2.7 to 3.6 V)
· 3.6 V tolerant inputs/outputs
· CMOS low power consumption
· Direct interface with TTL levels (2.7 to 3.6 V)
· Power-down mode
· Latch-up performance exceeds 250 mA
· ESD protection:
  HBM EIA/JESD22-A114-A exceeds 2000 V
  MM EIA/JESD22-A115-A exceeds 200 V.


Specifications

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage   -0.5 +4.6 V
IIK input diode current VI < 0 - -50 mA
VI input voltage   -0.5 +4.6 V
IOK output diode current  VO > VCC or VO < 0 - ±50 mA
VO output voltage enable mode; notes 1 and 2 -0.5 VCC + 0.5 V
disable mode -0.5 +4.6 V
Power-down mode; note 2 -0.5 +4.6 V
IO output source or sink current VO = 0 to VCC - ±50 mA
ICC, IGND VCC or GND current   - ±100 mA
Tstg storage temperature   -65 +150 °C
Ptot power dissipation
SO package		 above 70 °C derate linearly with
8 mW/K		 - 500 mW
TSSOP package above 60 °C derate linearly with
5.5 mW/K		 - 500 mW

Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. When VCC = 0 V (Power-down mode), the output voltage can be 3.6 V in normal operation.




Description

The 74ALVC125 is a high-performance, low-power,low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.

Schmitt-trigger action of the 74ALVC125 at all inputs makes the circuit tolerant for slower input rise and fall times.

The 74ALVC125 consists of four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH on pin nOE causes the outputs to assume a high-impedance OFF-state




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