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74ALS273

Features: • Eight edge-triggered D-type flip-flops• Buffered common clock• Buffered asynchronous master reset• See 74ALS377 for clock enable version• See 74ALS373 for transparent latch version• See 74ALS374 for 3-State versionPinoutSpecifications SYMBOL ...

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SeekIC No. : 004249299 Detail

74ALS273: Features: • Eight edge-triggered D-type flip-flops• Buffered common clock• Buffered asynchronous master reset• See 74ALS377 for clock enable version• See 74ALS373 for t...

74ALS273 Data Sheet

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Part Number:
74ALS273
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

• Eight edge-triggered D-type flip-flops
• Buffered common clock
• Buffered asynchronous master reset
• See 74ALS377 for clock enable version
• See 74ALS373 for transparent latch version
• See 74ALS374 for 3-State version


Pinout

Connection Diagram


Specifications

SYMBOL
PARAMETER
RATING
UNIT
VCC
 Supply voltage
0.5 to +7.0
V
VIN
 Input voltage
0.5 to +7.0
V
IIN
 Input current
30 to +5
mA
VOUT
 Voltage applied to output in High output state
0.5 to VCC
V
IOUT
 Current applied to output in Low output state
48
mA
Tamb
 Operating free-air temperature range
0 to +70
°C
Tstg
 Storage temperature range
65 to +150
°C



Description

The 74ALS273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously.

The register of the 74ALS273 is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition, is transferred to the corresponding flip-flop's Q output.

All outputs of the 74ALS273 will be forced Low independently of clock or data inputs by a Low voltage level on the MR input.

The 74ALS273 is useful for applications where the true output only is required and the CP and MR are common to all flip-flops.




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