Features: • Synchronous counting and loading
• Two count enable inputs for n-bit cascading
• Positive edge-triggered clock
• Asynchronous reset (74ALS161B)
• Synchronous reset (74ALS163B)
• High speed synchronous expansion
• Typical count rate of 140MHzPinout
Specifications
| SYMBOL |
PARAMETER |
RATING |
UNIT |
| VCC |
Supply voltage |
0.5 to +7.0 |
V |
| VIN |
Input voltage |
0.5 to +7.0 |
V |
| IIN |
Input current |
30 to +5 |
mA |
| VOUT |
Voltage applied to output in High output state |
0.5 to VCC |
V |
| IOUT |
Current applied to output in Low output state |
16 |
mA |
| Tamb |
Operating free-air temperature range |
0 to +70 |
°C |
| Tstg |
Storage temperature range |
65 to +150 |
°C |
DescriptionSynchronous presettable 4-bit binary counters (74ALS161B, 74ALS163B) feature an internal carry look-ahead and can be used for high speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock. The clock input is buffered.
The outputs of the counters of the 74ALS161B may be preset to High or Low level. A Low level at the parallel enable (PE) input disables the counting action and causes the data at the D0 D3 inputs to be loaded into the counter on the positive-going edge of the clock (provided that the setup and hold requirements for PE are met). Preset takes place regardless of the levels at count enable (CEP, CET) inputs. A Low level at the master reset (MR) input sets all the four outputs of the flip-flops (Q0 Q3) in 74ALS161B to Low levels, regardless of the levels at CP, PE, CET and CEP inputs (thus providing an asynchronous clear function).
For the 74ALS161B the clear function is synchronous. A Low level at the synchronous reset (SR) input sets all four outputs of the flip-flops (Q0 Q3) to Low levels after the next positive-going transition on the clock (CP) input ( provided that the setup and hold time requirements for SR are met). This action occurs regardless of the levels at CP, PE, CET and CEP inputs. The synchronous reset feature of the 74ALS161B enables the designer to modify the maximum count with only one external NAND gate (see Figure 1).
The carry look-ahead simplifies serial cascading of the counters of the 74ALS161B. Both count enable (CEP and CET) inputs must be High to count. The CET input is fed forward to enable the TC output. The TC output thus enabled will produce a High output pulse of a duration approximately equal to the High level output of Q0. This pulse can be used to enable the next cascaded stage (see Figure 2). The TC output of the 74ALS161B is subjected to decoding spikes due to internal race conditions, Therefore, it is not recommended for use as clock or asynchronous reset for flip-flops, registers, or counters.
74ALS161B Data Sheet
