Specifications SYMBOL PARAMETER Value Unit VCC Supply voltage -0.5 to +7.0 V VIN Input voltage -0.5 to +7.0 V IIN Input current 30 to +5 mA VOUT Voltage applied to output in High output state -0.5 to VCC V IOUT Current applied to output in Low output state 16 ...
74ALS112A: Specifications SYMBOL PARAMETER Value Unit VCC Supply voltage -0.5 to +7.0 V VIN Input voltage -0.5 to +7.0 V IIN Input current 30 to +5 mA VOUT Voltage applied to outp...
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Buffers & Line Drivers 16-Bit Buffer/Driver With 3-State Outputs
SYMBOL | PARAMETER | Value | Unit |
VCC | Supply voltage | -0.5 to +7.0 | V |
VIN | Input voltage | -0.5 to +7.0 | V |
IIN | Input current | 30 to +5 | mA |
VOUT | Voltage applied to output in High output state | -0.5 to VCC | V |
IOUT | Current applied to output in Low output state | 16 | mA |
Tamb | Operating free-air temperature range | 0 to +70 | |
Tstg | Storage Temperature | -65 to +150 |
The 74ALS112A, dual negative edge-triggered JK-type flip-flop features individual J, K, clock (CPn), set (SD), and reset (RD) inputs, true (Qn) and complementary (Qn) outputs.
The SD and RD inputs of the 74ALS112A, when Low, set or reset the outputs as shown in the function table regardless of the level at the other inputs.
A High level on the clock (CPn) input enables the J and K inputs and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CPn is High and the flip-flop will perform according to the function table as long as minimum setup and hold times are observed. Output changes are initiated by the High-to-Low transition of the CPn.