Features: · ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V· Balanced propagation delays· All inputs have Schmitt-trigger actions· Multiple input enable for easy expansion· Ideal for memory chip select decoding· Inputs acce...
74AHCT157: Features: · ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V· Balanced propagation delays· All inputs have Schmitt-trigger a...
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SYMBOL | PARAMETER |
CONDITIONS |
MIN. |
MAX. |
Unit |
VCC | DC supply voltage |
-0.5 |
+7.0 |
V | |
VI | input voltage range |
-0.5 |
+7.0 |
V | |
IIK | DC input diode current |
VI < -0.5 V; note 1 |
- |
-20 |
mA |
IOK | DC output diode current |
VO < -0.5 V or VO > VCC + 0.5 V; note 1 |
- |
±20 |
mA |
IO | DC output source or sink current |
-0.5 V < VO < VCC + 0.5 V |
- |
±25 |
mA |
ICC | DC VCC or GND current |
- |
±75 |
mA | |
Tstg | storage temperature range |
-65 |
+150 |
||
PD | power dissipation per package |
for temperature range: -40 to +125 °C; note 2 |
- |
500 |
mW |
The 74AHCT157 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.
The 74AHCT157 are quad 2-input multiplexers which select 4 bits of data from two sources under the control of a common data select input (S). The enable input (E) is active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all other input conditions.
Moving the data from two groups of registers to four common output buses is a common use of the '157'. The state of the common data select input (S) determines the particular register from which the data comes. It can also be used as a function generator.
The 74AHCT157 is useful for implementing highly irregular logic by generating any four of the 16 different functions of two variables with one variable common.
The '157' is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determine by the logic levels applied to S.
The logic equations are:
1Y = E ´ (1I1 * S + 1I0 *S);
2Y = E ´ (2I1 * S + 2I0 *S);
3Y = E ´ (3I1 * S + 3I0 * S);
4Y = E ´ (4I1 * S + 4I0 * S).
The '157' is identical to the '158' but has non-inverting (true) outputs.