74AHC74D

Maximum Operating Temperature : + 125 C
Mounting Style : SMD/SMT
Supply Voltage - Max : 5.5 V
Number of Circuits : 2
Input Type : Single-Ended
Packaging : Tube
Polarity : Inverting/Non-Inverting
Output Type : Differential
Low Level Output Current : 8 mA
Logic Type : D-Type Edge Triggered Flip-Flop
High Level Output Current : - 8 mA
Logic Family : AHC
Package / Case : SOT-108
Propagation Delay Time : 3.7 ns at 5 V


Description

The 74AHC74D belongs to 74AHC/AHCT74. The 74AHC/AHCT74 dual positive-edge triggered, D-type flip-flops with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs. The 74AHC/AHCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

The features of 74AHC74D can be summarized as (1)ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V, MM EIA/JESD22-A115-A exceeds 200 V; (2)balanced propagation delays; (3)inputs accepts voltages higher than VCC; (4)for AHC only: operates with CMOS input levels; (5)for AHCT only: operates with TTL input levels; (6)output capability: standard; (7)ICC category: flip-flops; (8)specified from -40 to +85 and +125 °C.

The absolute maximum ratings of 74AHC74D are (1)VCC DC supply voltage: -0.5 to +7.0 V; (2)VI input voltage: -0.5 to +7.0 V; (3)IIK DC input diode current (VI < 0.5 V; note 1): -20 mA; (4)IOK DC output diode current (VO < 0.5 V or VO > VCC + 0.5 V; note 1): ±20 mA; (5)IO DC output source or sink current (0.5 V < VO < VCC + 0.5 V): ±25 mA; (6)ICC DC VCC or GND current: ±75 mA; (7)Tstg storage temperature: -65 to +150°C; (8)PD power dissipation per package (for temperature range: 40 to +85 °C; note 2): 500 mW. (1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO packages: above 70 °C the value of PD derates linearly with 8 mW/K. For TSSOP packages: above 60 °C the value of PD derates linearly with 5.5 mW/K.)