74AHC573

The 74AHC573 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No.7A.

The 74AHC573 are octal D-type transparent latches featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A Latch Enable (LE) input and an Output Enable( OE</a>)input are commontoall latches.

The'573'consists ofeight D-type transparent latches with 3-state true outputs. When LE is HIGH,data at the Dn inputs enters the latches.In this condition the latches are tran sparent, i.e. a latch output will change state each time its corresponding D-input changes.

When LE is LOW the latches store the information of the 74AHC573 that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE.When OE</a> is LOW,the contents of the 8 latches are availableat the outputs.When OE</a>is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE</a> input does not affect the state of the latches. The'573'isfunctionallyidenticaltothe'533','563'and'373',butthe'533'and '563' have inverted outputs and the '563' and '373' have a different pin arrangement.