74AHC373

The 74AHC373 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no.7A.

The 74AHC373 are octal D-type transparent latches featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A Latch Enable(LE) input and an Output Enable(OE</a>) input are common to all latches.

The'373'consists of eight D-type transparent latches with  3-state true outputs. WhenLE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D-input changes.

WhenLE is LOW the latches store the information of the 74AHC373 that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition ofLE. When OE</a> is LOW, the contents of the 8latches are available at the outputs. When OE</a> is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE</a> input does not affect the state of the latches.

The '373' is functionally identical to the '533', '563' and '573',butthe'533'and'563'have inverted outputs and the '563' and '573' have a different pin arrangement.