74AHC273

The 74AHC273 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.

The 74AHC273 have eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs.

The common clock(CP)and master reset(MR</a>)inputs load and reset (clear) all flip-flops simultaneously.

The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Q_n) of the flip-flop.

All outputs of the 74AHC273 will be forced LOW independently of clock or data inputs by a LOW on the MR</a> input.

The 74AHC273 is useful for applications where the true output only is required and the clock and master reset are common to all storage elements.