74AHC257

The 74AHC257 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.

The 74AHC257 has four identical 2-input multiplexers with 3-state outputs, which select 4 bits of data from two sources and are controlled by a common data select input (S).

The data of the 74AHC257 inputs from source 0 (1I₀ to 4I₀) are selected when input S is LOW and the data inputs from source 1 (1I₁ to 4I₁) are selected when S is HIGH. Data appears at the outputs (1Y to 4Y) in true (non-inverting) form from the selected inputs.

The 74AHC257 is the logic implementation of a 4-pole 2-position switch, where the position of the switch is determined by the logic levels applied to S. The outputs are forced to a high impedance OFF-state when OE is HIGH.

If OE is LOW then the logic equations for the outputs are:

1Y = 1I₁ * S+1I₀ * S;

2Y = 2I₁ * S+2I₀ * S;

3Y = 3I₁ * S+3I₀ * S;

4Y = 4I₁ * S+4I₀ * S.

The '257' is identical to the '258' but has non-inverting (true) outputs.