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74AHC164

Features: · ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V· Balanced propagation delays· All inputs have Schmitt-trigger actions· Inputs accept voltages higher than VCC· For AHC only: operates with CMOS input levels· For A...

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SeekIC No. : 004249160 Detail

74AHC164: Features: · ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V· Balanced propagation delays· All inputs have Schmitt-trigger a...

74AHC164 Data Sheet

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Part Number:
74AHC164
Supply Ability:
5000

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  • 1~5000
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  • 15 Days
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Product Details

Description



Features:

· ESD protection:
  HBM EIA/JESD22-A114-A exceeds 2000 V
  MM EIA/JESD22-A115-A exceeds 200 V
  CDM EIA/JESD22-C101 exceeds 1000 V
· Balanced propagation delays
· All inputs have Schmitt-trigger actions
· Inputs accept voltages higher than VCC
· For AHC only: operates with CMOS input levels
· For AHCT only: operates with TTL input levels
· Specified from -40 to +85 °C and from -40 to +125 °C.


Pinout

Connection Diagram


Specifications

In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC DC supply voltage   -0.5 +7.0 V
VI input voltage   -0.5 +7.0 V
IIK DC input diode current VI < -0.5 V; note 1 - -20 mA
IOK DC output clamping diode
current		 -0.5 > VO > VCC + 0.5 V; note 1 - ±20 mA
IO DC output sink current -0.5 < VO < VCC + 0.5 V - ±25 mA
ICC DC VCC or GND current   - ±75 mA
Tstg storage temperature   -65 +150 °C
PD power dissipation per package for temperature range: -40 to +125 °C; note 2 - 500 mW

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO packages: above 70 °C the value of PD derates linearly by 8 mW/K.
For TSSOP packages: above 60 °C the value of PD derates linearly by 5.5 mW/K.


Description

The 74AHC164 shift registers are high-speed silicon-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.

The 74AHC164 input signals are 8-bit serial through one of two inputs (Dsa or Dsb); either input can be used as an active HIGH enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied HIGH.

Data shifts one place to the right on each LOW-to-HIGH transition of the clock (CP) input and enters into Q0, which is a logical AND of the two data inputs (Dsa, Dsb) that existed one set-up time prior to the rising clock edge.

A LOW level on the master reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all outputs LOW.




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