74AHC138D

Encoders, Decoders, Multiplexers & Demultiplexers 3-8 LINE DECDR/DEMUX INVERT

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SeekIC No. : 00425732 Detail

74AHC138D: Encoders, Decoders, Multiplexers & Demultiplexers 3-8 LINE DECDR/DEMUX INVERT

floor Price/Ceiling Price

Part Number:
74AHC138D
Mfg:
NXP Semiconductors
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/7/15

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Product Details

Quick Details

Product : Decoder / Demultiplexer Logic Family : AHC
Supply Voltage - Max : 5.5 V Supply Voltage - Min : 2 V
Maximum Operating Temperature : + 125 C Mounting Style : SMD/SMT
Package / Case : SOT-109 Packaging : Tube    

Description

Number of Bits :
Number of Lines (Input / Output) :
Propagation Delay Time :
Supply Voltage - Min : 2 V
Maximum Operating Temperature : + 125 C
Mounting Style : SMD/SMT
Supply Voltage - Max : 5.5 V
Product : Decoder / Demultiplexer
Packaging : Tube
Package / Case : SOT-109
Logic Family : AHC


Description

The 74AHC138D belongs to the 74AHC/AHCT138 family which are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The '138' features three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. The 74AHC138D decoders accept three binary weighted address inputs (A0, A1 and A2) and when enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7). This multiple enable function allows easy parallel expansion of the '138' to a 1-of-32 (5 to 32 lines) decoder with just four '138' ICs and one inverter. The '138' can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state. The '138' is identical to the '238' but has inverting outputs.

The features of 74AHC138D can be summarized as (1)ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V, MM EIA/JESD22-A115-A exceeds 200 V, CDM EIA/JESD22-C101 exceeds 1000 V; (2)balanced propagation delays; (3)all inputs have schmitt-trigger actions; (4)multiple input enable for easy expansion; (5)ideal for memory chip select decoding; (6)inputs accept voltages higher than VCC; (7)for AHC only: operates with CMOS input levels; (8)for AHCT only: operates with TTL input levels; (9)specified from -40 to +85 and +125 °C.

The absolute maximum ratings of 74AHC138D are (1)VCC DC supply voltage: -0.5 to +7.0V; (2)IIK DC input diode current (VI < -0.5 V; note 1): -20mA; (3)VI DC input voltage3: -0.5 to +7.0 V; (4)IOK DC output diode current(VO < -0.5 V or VO > VCC + 0.5 V; note 1): ±20mA; (5)IO DC output source and sink current( -0.5 V < VO < VCC + 0.5 V): ±25mA; (6)ICC DC VCC or GND current: ±75 mA; (7)Tstg storage temperature range: -65 to 150 °C; (8)PD power dissipation per package(for temperature range: -40 to +125 °C; note 2): 500mW(1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO packages: above 70 °C the value of PD derates linearly with 8 mW/K. For TSSOP packages: above 60 °C the value of PD derates linearly with 5.5 mW/K.).




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