74AHC138

The 74AHC138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No.7A.The 74AHC/AHCT138 decoders accept three binary weighted address inputs (A0,A1 and A2) and when enabled, provide8 mutually exclusive active LOW outputs (Y₀ to Y₇).

The  74AHC138 has features three enable inputs: two active LOW(E1 and E2 ) and one active HIGH (E3 ). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH.This multiple enable function allows easy parallel expansion of the  AE138 to 1-of-32 (5 to 32 lines) decoder with just four AE138 O ICs and one inverte. The  AE138 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and there maining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state.The AE138 O is identical to the AE238 O but has inverting outputs.