Features: •ESD protection:HBMEIA/JESD22-A114-Aexceeds 2000VMMEIA/JESD22-A115-Aexceeds 200VCDMEIA/JESD22-C101exceeds 1000V•Balanced propagation delays•All inputs have Schmitt-trigger actions•Inputs accepts voltages higher than VCC•For AHC only: operates with CMOS input...
74AHC126: Features: •ESD protection:HBMEIA/JESD22-A114-Aexceeds 2000VMMEIA/JESD22-A115-Aexceeds 200VCDMEIA/JESD22-C101exceeds 1000V•Balanced propagation delays•All inputs have Schmitt-trigge...
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The 74AHC126 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard No.7A.
The 74AHC126 are four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE) A LOW at nOE causes the outputs to assume a HIGH-impedance OFF state.
The '126' is identical to the '125' but has active HIGH enable inputs.