74AHC02PW

The 74AHC02PW belongs to 74AHC/AHCT02 family which are high-speed Si-gate CMOS devices and are pin compatible with low power schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT02 provides the quad 2-input or function.

The features of 74AHC02PW can be summarized as (1)ESD protection: HBM EIA/JESD22-A114-A, exceeds 2000 V; MM EIA/JESD22-A115-A, exceeds 200 V; CDM EIA/JESD22-C101, exceeds 1000 V; (2)balanced propagation delays; (3)all inputs have schmitt-trigger actions; (4)inputs accepts voltages higher than VCC; (5)for AHC only: operates with CMOS input levels; (6)for AHCT only: operates with TTL input levels; (7)specified from -40 to +85 and +125 °C.

The absolute maximum ratings of 74AHC02PW are (1)VCC DC supply voltage: ±0.5 to +7.0 V; (2)±IIK DC input diode current(VI < -0.5; note1): -20mA; (3)±IOK DC output diode current(VO < -0.5 or VO > VCC + 0.5V, note1): ±20mA; (4)IO DC output source or sink current-standard outputs(-0.5V < VO < VCC + 0.5V): ±25mA; (5)ICC DC VCC or GND current for types with-standard outputs: ±75mA; (6)Tstg storage temperature range: -65 to +150 °C; (7)PD power dissipation per package(for temperature range: -40 to +125°C, note2): 500mW.(NOTES: 1. The input and output voltage ratings of the 74AHC02PW may be exceeded if the input and output current ratings are observed. 2. For SO packages: above 70 °C the value of PD derates linearly with 8 mW/K. For TSSOP packages: above 60 °C the value of PD derates linearly with 5.5 mW/K.).